The present invention relates to a printed circuit board wiring method and more particularly to such type of method that is suitable for performing an open circuit or insulation test on a printed circuit board designed by new high-density layout technology applicable for the mounting of surface devices or the use of small vias on the printed circuit board.
For example, in the case of a printed circuit board for use with small-sized main frames and terminals, it is an urgent need to improve the layout density of electronic parts for the sake of economy and reliability. To this end, new layout techniques for the mounting of surface devices and the use of small vias which can not match the conventional grid (e.g., 100 mils grid) are employed. However, the printed circuit board which is designed by these new techniques can not be tested by the conventional testing method in which the probe pins are simultaneously brought into contact with all the lands provided on a 100 mils grid.
For wiring a printed circuit board having electronic parts mounted thereon with the intervals among the pins of the parts unmatched to the above-mentioned grid resolution, the following methods used in the Integri-Test 4500 system of the KOLLMORGEN CORPORATION are known. That is, (i) a method in which two probe pins are used to check whether or not the wiring between the lands are open-circuited; and (ii) a method in which a printed circuit board is placed on a conductive flat plate through an insulating material and the capacitance between lands on the board and the plate is detected to check whether or not any insulation fault exists in the printed circuit board.
According to the above-mentioned methods, it has been possible to detect an open circuit between wiring lands arranged at a desired interval of larger than a predetermined value since the probe pin can be moved to a desired position. However, the methods have had difficulties in that since the probe pins must be moved every time when the connection between every two lands is checked, it takes much time to test a large sized printed circuit board. Moreover, these methods have had a further difficulty in that when an insulation fault is inspected, the capacitance to be detected therefor varies depending on the thickness and quality of the insulating material so that no complete accuracy of analysis of faulty insulation is assured.
To describe concretely the problems involved in the open circuit test on a printed circuit board, we must first of all mention that there are, as parts not matching a grid resolution (e.g., 100 mil. 2.54 mm), a SOP (Small Outline Package), a FPP (Flat Plastic Package), a PLCC (Plastic Leaded Chip Carrier), and a S-DIP (Shrink-Dual Inline Package) shown in FIGS. 8 (a), (b), (c) and (d), respectively. These parts are attached to part mounting lands designated by reference numeral 2 in FIGS. 9 (a) to (d). However, the interval between pins of an electronic part or that between part mounting lands do not in many cases match a 100 mil grid and therefore, in case lands to mount different parts in a CAD system are wired, especially in the case of two channels between grid portions shown in FIG. 10 (wherein the grid portions are defined by blank circles, respectively, and the channels are designated by dotted lines running vertically and horizontally), a wiring pattern 3 is led out up to the cross point of the channels located near each of the lands, a wiring pin 4a is arranged at the position where the pattern 3 is led out, and is connected to another wiring pin 4b with a wiring pattern 5. Thus, in case a continuity test is conducted by the conventional method on a printed circuit board having wiring pins optionally arranged near the part mounting lands, respectively, it takes much time because, according to the method, all the probe pins must be brought into contact with the lands on the 100 mil grid while the intervals among the lands on the circuit board are not definite. This is especially so when the circuit board is large-sized.